Tech Expert Panel: AI-Driven SoC Verification

Moores Lab AI

Breker and Moores Lab AI will be hosting an evening reception where we will discuss the next frontier of AI-Driven Verification for SoCs.

Hyatt Regency Santa Clara

After Day 1 of DVCon, join us in the Cypress Room of the Hyatt for an exciting panel discussion and some happy hour refreshments.The use of AI for verification is already showing great promise, particularly in the area of specification comprehension leading to test generation for UVM IP verification. However, SoC verification represents another leap forward in requirements and complexity. SoC tests combine C-code for processor firmware synchronized with transactions for IO. They must track unpredictable corner cases over complex architectures. They must run on multiple verification platforms. Many of these issues have been solved with then use of Test Suite Synthesis. Leveraging AI to convert specifications to test models combined with synthesis to drive SoC multi-test coverage seems the way to go. The panel will consider the SoC issues they are seeing and how AI and synthesis can be used to target this next verification frontier.Moderated by: Bernard Murphy, Editor, SemiWikiPanelists: Shelly Henry, CEO, Moores Lab AI Adnan Hamid, CTO, Breker Verification Systems Deepak Manoharan, Senior Director, Arm Michael Chin, Senior Principal Engineer, Intel Corp

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Tech Expert Panel: AI-Driven SoC Verification

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Tech Expert Panel: AI-Driven SoC Verification

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