Parallel Programming Workshop 2017

Zuse Institute Berlin (ZIB)

<H2 CLASS="MsoNormal">Speedup Your Code on Intel® Xeon Phi™ and Xeon™ Processors at HLRN</H2>
Current Intel® Xeon Phi™ processors (Knights Landing - KNL) and next-generation Intel® Xeon™ CPUs feature increasing core counts, integration of high-bandwidth memory (Xeon Phi), and wider SIMD units (AVX-512). Existing codes need to be modernized to take full advantage of the architectural features of these CPUs. Newly developed code should be designed to do so from the beginning.
We invite code developers to the workshop on advanced code optimization techniques on state-of-the-art and tomorrow's multi- and many-core processors.
 
<H3>DRAFT AGENDA </H3>
<H4>20.03.2017,  13:00 - 18:00:</H4>
<UL>
<LI>Features of the Intel Xeon Phi and Xeon CPU architectures </LI>
<LI>Advanced optimization techniques: vectorization for AVX512 and thread-parallelism with OpenMP </LI>
<LI>Using the Intel and Cray compiler</LI>
<LI>Advanced features of the Intel VTune performance analysis tool</LI>
<LI>"Hackathon": bring your own code and start modernizing it</LI>
</UL>
<H4> </H4>
<H4>21.03.2017, 09:00 - 18:00:</H4>
<UL>
<LI>"Hackathon" (cont.)</LI>
<LI>Using the Cray tools CrayPAT and Reveal for code optimization</LI>
<LI>Hands-on-Sessions with example codes (alternative)</LI>
<LI>Q&A session and discussion, lessons learned </LI>
</UL>
<H4> </H4>
<H4>22.03.2017, 09:00 - 12:00:</H4>
<UL>
<LI>"Hackathon" (cont.), Hands-on-Sessions, Q&A session and discussion, lessons learned </LI>
</UL>
 
<H3 CLASS="MsoNormal">Start Optimization Work Now</H3>
The Hackathon provides the unique opportunity to start or continue the optimization work with the assistance of experts from ZIB, Intel and Cray. Therefore, we highly recommend that the attendees bring their own codes, kernels or proxy benchmarks to the workshop. For the Hackathon, the HLRN resources at ZIB, i.e. the Cray TDS with 80 Intel KNL nodes and the Cray XC40/XC30 system with Intel Haswell/Ivybridge nodes are open for code evaluation, optimization and benchmarking. Attendees with a valid HLRN account can transfer their codes to the HLRN system in Berlin in advance.
Workshop Presenters and Hackathon Support 
Presentations and the support in the Hackathon sessions are given by the IPCC@ZIB team and experts from Intel and Cray.
<H3 CLASS="MsoNormal">Registration</H3>
The workshop is open for the HLRN community and members of public funded academic institutions. Please register with your official business email address. 
<H3 CLASS="MsoNormal">Contact</H3>
For further questions please contact Thomas Steinke at <A HREF="mailto:steinke@zib.de" TARGET="_blank" REL="nofollow noopener noreferrer">steinke@zib.de</A> .

Zuse Institute Berlin

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Parallel Programming Workshop 2017

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Parallel Programming Workshop 2017

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