Workshop theme: We would like to explore the state-of-the art in compilers for machine learning in this series of workshops. In our Fall 2018 workshop, we featured the speakers from teams working on Google Tensorflow XLA, Intel nGraph & PlaidML, TVM and Xilinx ML Suite. In this Spring 2019 workshop, we would be featuring speakers who are working in areas such as Facebook Glow, Cadence's XNNC (Tensilica Xtensa Neural Net Compiler), and LeFLow - an open-source tool-flow that maps numerical computation models written in Tensorflow to synthesizable hardware. The talks are focused on explaining the design choices as well as hands-on overview of how to get started on these compilers to contribute.

Background for workshop theme:

Designing new models is currently driven by automated search or human expert guided search for exploring model architectures and hyperparameters. Training these models takes a significant amount of computer resources and time as well as larger training data sets. The current way of optimizing inference models is to take these larger models/neural networks and then attempt to simplify them through pruning. One of the open problems in machine learning is building optimal networks while using less training data. Another open problem in machine learning is designing networks that can learn from a mix of information (text, audio, images and side channel information) to more abstraction of understanding of what is happening in scene. These problems need major breakthroughs and need a holistic understanding of several scientific disciplines including information theory, neuroscience.

There is also a new focus on new computing and memory architectures that can address the limitations of traditional computing for current as well as emerging machine learning workloads. These architectures require new compilation techniques. While, it is potentially possible to brew a customized compiler that does not have any dependencies on the open source compilers such as LLVM for a given dataflow architecture or accelerator, given the speed at which machine learning models and workloads are evolving, the needed dataflow architectures to run these models are expected to be in flux as well. So there is a critical need for a compiler framework that can support machine learning accelerators.

Event Schedule:

• 1:30-2pm: Check-in

• 2-3pm: Talk by Nadav Rotem on Facebook Glow

• 3-3:15pm: Coffee break

• 3:15-4:15pm: Talk by Maxim Lukyanov on Cadence's XNNC (Tensilica Xtensa Neural Net Compiler),

• 4:15-4:30pm: Coffee break

• 4:30-5:30pm: Daniel Holanda Noronha from University of Britsh Columbia presents LeFLow, an open-source tool-flow that maps numerical computation models written in Tensorflow to synthesizable hardware.

If you have any suggestions on speakers or you want to speak at our next offerings of this work, please contact us through the form at the end.

Primary Organizer: IEEE Silicon Valley Artificial Intelligence Chapter (Santa Clara Valley Chapter of IEEE Computational Intelligence Society)

Co-Sponsored by Western Digital Research (Limited to providing venue and food and snack to attendees, video recording of the event if possible)

Western Digital Research :The core mission of the Research team in the CTO Office is to develop new technologies for future Western Digital products and businesses. We work on a wide range of emerging technologies, including storage-class memories, memory system architecture, high-performance storage architecture, machine-learning, RISC-V core microarchitecture, Linux kernel architecture, memory-centric compute, industry standards and security.

Co-sponsored by ValleyML.AI (for event publicity)

Valley Machine Learning (VML) is the most active and important community of AI Start-ups, Data Practitioners and Job-Seekers, Executives and Researchers. VML bring together business leaders and applied machine learning and deep learning practitioners.

Host/Program Chair: Dr. Kiran Gunnam

Venue: Western Digital, Building 2, 951 SanDisk Drive, Milpitas, California 95035

Admission fee: None.

Registration: By invite through Western Digital & IEEE. If you want to get an invite, please contact Dr. Kiran Gunnam through the Contact button below.