Speedup Your Code on Intel® Processors at HLRN

Recent Intel® Scalable processors (Skylake) and next-generation Intel® CPUs feature large core counts, wide SIMD units (AVX-512) and high-bandwidth memory (e.g. on Intel® Xeon Phi 7200 series - Knights Landing). Existing codes need to be modernized to take full advantage of the architectural features of these CPUs. Newly developed code should be designed to do so from the beginning.

We invite code developers to a workshop on advanced code optimization and programming techniques on today's and tomorrow's processors. We want to help you to make progress with optimizing your codes. The workshop's agenda is flexible. Please take 5 minutes to answer our survey and help us make the workshop worth your time.

See the Workshop Website for the preliminary Agenda.

Start Optimization Work Now

The Hackathon provides the unique opportunity to start or continue modernizing and optimization your code with the assistance of experts from ZIB and Intel. We highly recommend bringing your own codes, kernels or proxy benchmarks to the workshop. For the Hackathon, the HLRN resources at ZIB, i.e. a Cray TDS with 80 nodes with Intel® Xeon Phi™ 7200 series (KNL) CPUs and the Cray XC40/XC30 system with Intel® Xeon Haswell/Ivybridge nodes are open for code evaluation, optimization and benchmarking. Attendees with a valid HLRN account can transfer their codes to the HLRN system in Berlin in advance

Below are some links to help you in preparing your attendance:
- The HLRN system: - Quickstart Guide
- Get access to the HLRN system: DE / EN
- Material from previous workshops: Spring 2017, KNL Workshop 2016

Workshop Presenters and Hackathon Support

Presentations and the support in the Hackathon sessions are given by the IPCC@ZIB team and experts from Intel.

Registration

The workshop is open for the HLRN community and all members of publicly funded academic institutions. Please register with your official business e-mail address.

Contact

For further questions please contact Thomas Steinke (steinke@zib.de).

HLRN Parallel Programming Workshop Fall 2017