An Overview of Signal Integrity

The Santa Clara Valley Chapter of the IEEE Circuits and Systems Society focuses on the theory, analysis, design, practical implementation of circuits, and the application of circuit theory to systems and signal processing in industry and academia. The Chapter provides a forum where participants can network, learn and exhange ideas in a welcoming professional environment.

IEEE SCV CAS

Dr. Beyene will review the basics of signal integrity and important factors necessary to meet performance needs of the latest EE systems.

Cupertino Library, Conference Room 201

Talk Overview:Signal Integrity is critical to the design of high-performing and reliable semiconductor products. As the data rates increase rapidly in high-speed systems, the signal integrity has become a key factor to meet the bandwidth growth intensified by various applications. In this presentation, we will start with the review of the basics of signal integrity and examine the key electrical characteristics of interconnects: signal loss, signal crosstalk, return loss, mode conversion and other important factors necessary to meet the performance requirements of the latest electronic systems.Then, the interactions between the signaling, clocking, equalization and modulation of the various interfaces will be discussed to explain how those interactions determine the achievable data rates. Finally, the presentation will be concluded by reviewing various signal integrity modeling and simulation techniques.Short Bio:Dr. Wendem T. Beyene was born in Addis Ababa, Ethiopia. He received the B.S. and M.S. degrees in electrical engineering from Columbia University, New York, NY, USA, in 1988 and 1991, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, USA, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. In 2000, he joined Rambus Inc., Los Altos, CA, USA, and was responsible for signal integrity of multi-gigabit parallel and serial interfaces. During 2017-2020 he worked at Intel and was responsible for signal and power integrity analysis of high-performance FPGA including fabric and high-speed I/O subsystems as well as I/O modeling. In 2020 he joined Facebook (Meta Platforms) as an Analog &amp; Mixed-Signal Architect in Meta Reality Lab.Dr. Beyene has authored numerous refereed IEEE publications in various disciplines including package and interconnect modeling, interface design and analysis as well as application of machine learning and optimization techniques to signal and power integrity of complex systems. He is currently a Senior Area Editor - Electrical Performance of Integrated Systems of IEEE Trans. On CPMT and is a Senior Member of IEEE. He also has served as distinguished lecturer for IEEE EMCS (Electromagnetic Compatibility Society) and IEEE EPS (Electrical Packaging Society).