Thermal Atomic Layer Etch f/ Logic Memory Downscaling WALK-IN NOT SOLD OUT

IEEE SFBA Nanotechnology Council Chapter

San Francisco Bay Area IEEE Nanotechnology Council

EAG Laboratories

San Francisco Bay Area IEEE Nanotechnology Council2020, 2017 &amp; 2014 Nanotechnology Council Outstanding Chapter (world-wide)2019, 2016 &amp; 2014 IEEE Outstanding Chapter (Western USA)2019, 2016 IEEE Outstanding Chapter (Santa Clara Valley)<a href="http://sites.ieee.org/sfbanano" title="http://sites.ieee.org/sfbanano" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">http://sites.ieee.org/sfbanano</a> <h1>Thermal Atomic Layer Etch for Logic and Memory Downscaling</h1><h3>Martin McBriarty</h3><h3>Senior Scientist, EMD Electronics</h3> <h3>In-Person Meeting</h3>Thursday, April 11, 202411:30 AM: Networking, Pizza &amp; DrinksNoon -- 1 pm: SeminarPlease register on Eventbrite before 9:30 AM on Thursday, April 11 , 2024Walk-In attendance is welcomed but discouragedPlease assist us in our event planning!If you decide not to attend... - please cancel reservations by 8:00 AM on Thursday, ** Tickets cancelled by 8 AM on April 11 will have payments refunded*** Note: Eventbrite Fees will not be refunded Location:EAG Laboratories;810 Kifer Road, Sunnyvale==&gt; Use corner entrance: Kifer Road / San Lucar Court==&gt; Do not enter at main entrance on Kifer Road(Parking: on street or in parking lot behind EAG)

<h3>Abstract:</h3> <h3>As downscaling approaches physical limits, semiconductor devices are evolving into increasingly complex 3D nano-architectures. Fabricating these unprecedented devices in HVM requires precise and selective material deposition &amp; etch methods.</h3> <h3>Atomic layer etch (ALE) helps to sculpt these structures by selectively removing materials with angstrom-scale control. By exploiting chemical differences between materials, ALE processes are designed to etch certain exposed materials while minimizing damage to others. ALE can enable scaling boosters such as fully self-aligned via (FSAV), a critical method for logic back end of line (BEOL) downscaling. Vapor-phase thermal ALE can also provide controlled, selective etch in features with high aspect ratio, low critical dimension, or horizontal openings, overcoming the limitations of wet and plasma etches in emerging 3D structures.</h3> <h3>This seminar will focus on ALE of metals and metal oxides for logic and DRAM, including process fundamentals, selectivity mechanisms, and thermal ALE processes developed at EMD Electronics</h3>

<h3>Bio:</h3> <h3>Martin McBriarty</h3><h3>Senior Scientist, EMD Electronics</h3><h3> </h3><h3>Martin McBriarty leads atomic layer etch development at EMD Electronics in San Jose, California.</h3> <h3>He earned his B.S. in Materials Science &amp; Engineering at the University of Florida in 2008 and his Ph.D. in the same field at Northwestern University in 2014. He studied at the Fritz Haber Institute as a Fulbright scholar and completed postdoctoral work at Pacific Northwest National Laboratory before joining Intermolecular (a business of Merck KGaA, Darmstadt, Germany) in 2018.</h3>

If you have questions or problems with your registration, please contact <a href="mailto:LincolnBourne@gmail.com" title="mailto:LincolnBourne@gmail.com" target="_blank" data-msys-clicktrack="0" rel="nofollow noopener noreferrer">LincolnBourne@gmail.com</a>* Please help us manage our event planning. When we have many walk-in attendees, it is difficult for us to order the proper amount of food for lunch.** Tickets cancelled by 8 AM on April 11 will have payments refunded*** Note: Eventbrite Fees will not be refunded

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Thermal Atomic Layer Etch f/ Logic Memory Downscaling WALK-IN NOT SOLD OUT

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Thermal Atomic Layer Etch f/ Logic Memory Downscaling WALK-IN NOT SOLD OUT

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