3D Packaging for Superconducting Qubits

IEEE-Electronics Packaging Society/SCV

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Dr. R. N. Das, MIT Lincoln Laboratory<h2>Directions for connecting with the WebEx stream will be sent via email to all registrants 1-2 days prior to the event.</h2>11:50 AM - 12:00 PM: Check-in12:00 PM: Presentation  &amp; QAWE USUALLY GET PRESENTER SLIDE DECK, but sometimes not. When speaker provides it, in original or sanitized form, it will be uploaded at the chapter website - www.ieee.org/scveps.  Older presentation may also be accessed at same page. Summary: Superconducting qubits are a leading candidate for constructing a large-scale quantum processor due to their lithographic scalability and relatively long coherence times. 3D qubit packaging, enabling the integration of more chips with greater functionality, higher I/O counts, and smaller pad pitches – while maintaining qubit coherence – is critical for scalable computing architecture. In this talk, I will present a microbump-based assembly approach to produce three-tier stacks with a qubit chip on the top, superconducting multi-chip-module (SMCM) on the bottom, and an interposer chip with superconducting through-silicon vias (TSVs) in the middle. I will discuss our work developing a double bump-bonding process to create the qubit-interposer-SMCM stack, focusing on electrical characterization, alignment accuracy, spacing and co-planarity.[This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), the Defense Advanced Research Projects Agency (DARPA), and by the Assistant Secretary of Defense for Research &amp; Engineering under Air Force Contract No. FA8702-15-D-0001. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, DARPA, or the U.S. Government.]Bio:Rabindra N. Das is a Member of the Technical Staff in the Quantum Information and Integrated Nanosystems Group, MIT Lincoln Laboratory, Lexington, MA USA. Prior to MIT, he was a Principal Engineer at Endicott Interconnect Technologies (formerly IBM Endicott). Dr. Das has 18 years of experience in microelectronics packaging development for applications ranging from HPC to medical to quantum electronics. He holds 48 patents and more than 100 publications. Email Rabindra.Das@ll.mit.edu.- more chips, microbump-based assembly, three-tier stacks, alignment accuracy, co-planarity .....

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3D Packaging for Superconducting Qubits

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