Mudasir Ahmad, Advanced Technology Development & Reliability, Google

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11:50 AM - 12:00 PM: Check-in

12:00 PM: Presentation  & QA

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Summary:

Artificial Intelligence, Internet of Things, 5G, Industrie 4.0, Augmented Reality, TeleHealth, Cloud Computing and other applications are driving higher bandwidth and capacity and lower latency. The thirst for more data, compute and storage is driving silicon die sizes beyond reticle size; and the need to integrate multifunctional devices into a common substrate is driving physical miniaturization further. Heterogeneous integration is expected to help continue Moore’s (or More than Moore’s) Law. Unfortunately, the cost of transistor miniaturization is also increasing exponentially. For perspective, the cost of developing a 5nm die exceeds the cost of 7nm and 10nm die development cost combined (see figure).

The newer the process node and the larger the die, the lower the yield and more expensive it is to integrate. This naturally leads to the concept of splitting the die into smaller dies (chiplets), utilizing less compute-intensive compute processes (like I/O) on older silicon process nodes, and integrating multiple functions and IP from different sources on a common package substrate. While it may be difficult for chiplets to deliver the exceptional performance of a single monolithic die, in applications where overall performance and cost need to be balanced, chiplets can offer a more viable solution. Chiplets are also essential when the monolithic die size needs to be larger than the reticle size for higher performance. However, splitting the die can also reduce performance and add costs like Known Good Die (KGD) testing, IP interface latency and area, and advanced packaging. So when does disaggregating the die make sense? That depends on several factors and their tradeoffs to achieve an optimal, practical solution. While conceptually, most industry experts agree on the benefits of chiplets, knowing precisely how to split the die and balance performance with cost becomes the key challenge.

In this talk, we present an open economic model that anyone can utilize to determine if/when chiplets make sense and when they do not. While most large corporations have sophisticated wafer yield and cost models, having an open-source model that captures KGD, chiplet assembly steps, advanced packaging and overall yield can help speed up the decision-making process on chiplet integration. Such an open-source economic model can also help accelerate innovative technology investments and even open up newer business models to foray the costs of developing chiplets while delivering step function value. By attending this talk, you will achieve an understanding of what key factors need to be accounted for in deciding on chiplets and how the uncertainty of those factors can influence your design and business model options. You will be empowered with an open-source model that you can use to make your own decisions and tradeoffs so you can be better prepared for the consequences of those tradeoffs and achieve your business objectives faster.

Bio:

Mudasir Ahmad is currently working on Advanced Technology Development and Reliability at Google. Prior to that, he was a Distinguished Engineer/Senior Director at Cisco Systems, Inc. He has been involved with mechanical design, microelectronics packaging design, and reliability analysis for more than 20 years. Mudasir is involved in developing new analytical/stochastic algorithms, experimental design, thermal and reliability characterization of next-generation 3D packaging, System-in-Package Modules, Chiplets, and Silicon Photonics. Mudasir is also involved with implementing IoT, Artificial Intelligence, and Big Data Analytics to streamline Supply Chain Operations. Mudasir has delivered several invited talks on leading technology solutions internationally. Outside of Google, he is a Distinguished Lecturer of the Electronics Packaging Society of the IEEE (EPS) and participates in standards organizations and consortia such as IPC, JEDEC, and ODSA. He was actively involved in the local EPS chapter of IEEE for several years; holding the positions of Secretary, Vice-Chair, and Chair of the Chapter. He received the internationally renowned Outstanding Young Engineer Award in 2012 from the IEEE. He received his M.S. in Management Science & Engineering from Stanford University, his M.S. degree in Mechanical Engineering from Georgia Institute of Technology, and his B.S. from Ohio University. Mudasir has over 30 publications on microelectronic packaging, two book chapters, and 17 US Patents.

- HI, large die sizes, cost of miniaturization, balance, disaggregating, splitting the die, when chiplets make sense .. ...