Monolithic Co-integration of III-V Materials in Single Chip CMOS

Distinguished Lecturer Event: Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Dr. Xing Zhou.

When: Friday, June 27th, 2025 – 11:30AM to 1PM (PDT)

11:30AM - 12PM: Networking / Food

12PM-12:45PM: Lecture

12:45PM-12:55PM: Q&A

1PM Adjourn

Where: Rappi Room, Plug and Play Tech Center

440 N Wolfe Rd, Sunnyvale, CA 94085

This is an hybrid event and attendees can participate via Zoom. The Zoom meeting link will be sent a few days before the event to registered attendees.

Contact: ieeescveds at gmail.com

Speaker: Dr. Xing Zhou

Abstract:

As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. This talk presents an overview of the 10-year research program, which is a “vertical” innovative platform by “inserting” III-V layers into a conventional Si-CMOS foundry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology.

Speaker Bio:

Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His research at NTU mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 150 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference (2002–2018). He was an editor for the IEEE Electron Device Letters (2007–2016), a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecturer since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter.