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IEEE CASS-SCV Artificial Intelligence for Industry (AI4I) Forum - FALL2019

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Intel SC-9 Auditorium

2191 Laurelwood Rd

Santa Clara, CA 95054

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Description

CASS-SCV Artificial Intelligence for Industry (AI4I) Forum - Fall 2019

Event sponsored and organized by:

IEEE Circuits and Systems Society (CASS)

Co-sponsors:

DATE & TIME:

Friday, September 6th, 2019. 1 PM - 5 PM

PROGRAM:

1:00 - 1:30 PM Check-in / Networking & Refreshments

1:30 - 2:15 PM Prof. S.Y. Kung (Princeton)

2:15 - 3:00 PM Pete Warden (Google)

3:30 - 4:15 PM TBD

4:15 - 5:00 PM TBD

5:00 PM Adjourn

LOCATION:

Intel SC-9 Auditorium

2191 Laurelwood Rd, Santa Clara, CA 95054 (Northwest corner of 101 & Montague Expwy)

AGENDA:

1:30 - 2:15 PM Prof. S.Y. Kung (Princeton)

Kung

TITLE: From Deep Learning to X-Learning: An Internal and Explainable Learning for XAI

ABSTRACT: The success of deep Learning (or AI2.0) depends solely on Back-propagation (BP), a external learning paradigm, whose supervision is exclusively accessed via the external interfacing nodes (i.e. input/output neurons). As such, Deep Learning has been limited to the parameter training of the neural nets (NNs). The important task of designing optimal net structures has to resort to trial and error. Therefore, we shall design an Xnet which may be use to simultaneously train the structure and parameters of the net. In addition, it can facilitate Internal Neuron's Explainablility so as to fully support DARPA's Explainable AI (i.e. XAI or AI3.0). Our internal learning paradigm leads to an Explainable Neural Networks (Xnet) comprising (1) internal teacher labels (ITL) and (2) internal optimization metrics (IOM). X-learning allows us to effectively rank the internal neurons (hidden nodes) and thus sets the footing for the notion of structural gradient and structural learning.

Pursuant to our simulation studies, Xnet can simultaneously compress the structure and raise the accuracy. There is evidence supporting that it may outperform many popular pruning/compression methods. Most importantly, X-learning opens up promising research fronts on (1) explainable learning models for XAI and (2) machine-to-machine mutual learning which will become appealing in the 5G era

BIO: S.Y. Kung, Life Fellow of IEEE, is a Professor at Department of Electrical Engineering in Princeton University. His research areas include multimedia information processing, machine learning, systematic design of deep learning networks, VLSI array processors, and compressive privacy. He was a founding member of several Technical Committees (TC) of the IEEE Signal Processing Society. He was elected to Fellow in 1988 and served as a Member of the Board of Governors of the IEEE Signal Processing Society (1989-1991). He was a recipient of IEEE Signal Processing Society's Technical Achievement Award for the contributions on "parallel processing and neural network algorithms for signal processing" (1992); a Distinguished Lecturer of IEEE Signal Processing Society (1994); a recipient of IEEE Signal Processing Society's Best Paper Award; and a recipient of the IEEE Third Millennium Medal (2000). Since 1990, he has been the Editor-In-Chief of the Journal of VLSI Signal Processing Systems. He has authored and co-authored more than 500 technical publications and numerous textbooks including ``VLSI Array Processors'', Prentice-Hall (1988); ``Digital Neural Networks'', Prentice-Hall (1993) ; ``Principal Component Neural Networks'', John-Wiley (1996); ``Biometric Authentication: A Machine Learning Approach'', Prentice-Hall (2004); and ``Kernel Methods and Machine Learning”, Cambridge University Press (2014).

2:15 - 3:00 PM Pete Warden (Google)

TITLE: What Machine Learning Needs from Embedded Hardware
ABSTRACT:
This talk will cover the emerging requirements of deep learning workloads, including the barriers that are preventing more widespread deployment on low-energy systems. Many peculiar characteristics of machine learning include arithmetic intensity, robustness to noise and precision loss, and scalability, and these affect what the software layer expects from the underlying hardware. We'll discuss what has been learned over the last few years of deploying practical applications, and what is likely to be required in the future.

BIO: Pete Warden is a technical lead on the TensorFlow Lite team, responsible for embedded platforms. He was previously CTO of Jetpac, joining Google when it was acquired in 2014, and has worked at Apple on GPGPU processing.

3:30 - 4:15 PM TBD

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4:15 - 5:00 PM TBD

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Date and Time

Location

Intel SC-9 Auditorium

2191 Laurelwood Rd

Santa Clara, CA 95054

View Map

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