The Buck Stops Here: How accountability and ownership drive quality in FPGAs
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The Buck Stops Here: How accountability and ownership drive quality in FPGAs

The Buck Stops Here: How accountability and ownership drive quality in FPGA...

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Intel San Jose Campus (formerly Altera)

Building 3, Auditorium

101 Innovation Drive

San Jose, CA 95134

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The Quality Food Chain

Join the Women at Intel Network (WIN), San Jose chapter and IEEE Santa Clara Valley Women in Engineering (IEEE SCV WIE) for a panel discussion featuring the Intel Programmable Solutions Group discussing the quality “food chain” from Architecture and Marketing to Test and Tech Comms.



5:30 – 6:00: Check in, food and networking in the cafe

6:00 – 6:15: Message from our sponsors (auditorium)

6:15 – 7:15: Panel discussion

7:15 – 7:45: Wrap up and more networking

To ensure a smooth sign-in process, plan to arrive between 5:30pm and 6pm. Attendees will need receive a temporary badge from Intel security.

Panelist Profiles


Terry Barrette is the Director of Tester and Manufacturing Engineering for the Programmable Solutions Group reporting into the Intel-STTD (Sort Test Technology Development) group and is responsible for setting the direction on manufacturing tools and Tester Technology for this Business Unit. Terry has worked in the semiconductor industry for over 25 years progressing through a series of technical and leadership roles.


Tom Schulte joined Altera in 1994 and currently works in Altera's Low-Cost Products group as a Product Marketing Manager. In this capacity, Schulte is responsible for developing marketing strategies around Altera's Cyclone and MAX product families. Prior to Altera, he served as a product marketing engineer in IDT's Subsystems Division. Tom holds a BS in Electrical Engineering from Santa Clara University. Tom's extra-curricular interests include playing beach volleyball, volunteering, reading sci-fi, watching movies, and meeting new people.


Tara Clark, CAD Engineer at Intel Programmable Solutions Group (PSG), develops the architecture of the design data management infrastructure and leads implementation and testing of this platform. Major components of this system include the revision control layer; build, test and release platform; and metadata used to control the flow. In addition to her technical role, she led the Women@Altera employee resource group for over two years and remains actively involved as a member of the core leadership team of the newly created Women at Intel Network San Jose chapter. Tara enjoys helping with campus recruiting and the University Program.


Sangeeta Raste has worked at Altera for 13 years, now called Intel, PSG. She currenty works as a Ethernet IP and High speed transceiver PHY IP Developer in R&D organization. She has lead many hardware and software projects throughout her career. As a FPGA (Field Programmable Gate Array – FPGA is a device with programmability) design engineer; she writes Ethernet MAC IP, PHY level IPs in Verilog, VHDL, build logic designs, build silicon, bringup hardware and work with different FPGA Boards and gets to work on the cutting edge technology. She enjoys her work and tries to find innovative ways to make it more interesting.


Divya Mullassery is an SoC Design Engineer at Intel PSG and has been working here for the past 8 months. Prior to Intel, she has worked at Cswitch and Mosys in multiple roles. She is actively involved with Women at Intel and currently serves as one of the recruiting committee co-chairs at WIN-SJ. She holds an MS in Electrical Engineering from Syracuse University, New York. She has too many interests to list and loves to travel and meet new people.


Priya Rajachidambaram is a Layout Verification Lead at Intel PSG. She has a MSEE from University of Kentucky and 10+ years of industry experience in Layout verification software development. Her software quality perspectives are built from working at two design houses and a foundry. Her team’s work involves building FPGA-specific verification software, tuning foundry-developed verification software for FPGA needs while liaising with the circuit designers, layout designers and the foundry. Her team also supports the verification efforts and is involved in gate-keeping the quality of verification before layout reaches the foundry. In her spare time she enjoys hiking and cooking with her 5 year old daughter.

Geetha Rao is an ASIC/FPGA Design Verification Manager. Geetha has 12 years of experience in Semiconductor Industry, especially in ASIC Design, Verification and DFT.


This event is hosted by: WIN San Jose (formerly Women@Altera) and IEEE SCV Women in Engineering.

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Location

Intel San Jose Campus (formerly Altera)

Building 3, Auditorium

101 Innovation Drive

San Jose, CA 95134

View Map

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