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Recent Advances and Trends in Semiconductor Packaging - John H. Lau, Sr. Technical Advisor ASM

AM

Tuesday, April 12, 2016 from 11:30 AM to 1:30 PM (PDT)

Registration Information

Registration Type Sales End Price Fee Quantity
1: IEEE members: Refreshments and Talk   more info Ended $5.00 $0.00
2: non IEEE Members: Refreshments and Talk Ended $10.00 $0.00
3: Talk Only - (Please arrive by 11:45) [IEEE members: please enter membership info when prompted]   more info Ended Free $0.00

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Event Details

 
11:30 - 12PM: Check-in / networking - light lunch
 
12:00PM: Presentation.
 
Registration [refreshments and talk]:
 
IEEE Members:  $5.00
[also for students and unemployed]
 
non-IEEE members: $10.00
 
[This signs you up for talk too, please do not also register for Talk-Only]

 
Registration for Talk-Only: FREE
 
Talk-Only attendees: please check-in by 11:45

 

Summary:

Recent Advances and Trends in Semiconductor Packaging

 

Abstract
Recent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers),  embedded 3D hybrid integration (of  VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration are examined and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.
 

Short Bio
John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at Hewlett-Packard/Agilent for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 20 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration (2013), and 3D IC Integration and Packaging (2015). He is an IEEE Fellow and ASME Fellow.

 

CPMT  Packaging   Semiconductors

Have questions about Recent Advances and Trends in Semiconductor Packaging - John H. Lau, Sr. Technical Advisor ASM? Contact AM

When & Where


Texas Instruments Building E Conference Center
2900 Semiconductor Dr.
Santa Clara, CA 95054

Tuesday, April 12, 2016 from 11:30 AM to 1:30 PM (PDT)


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