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Memory and Interfaces for AI and Hyperscale Computing

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Rambus Inc

1050 Enterprise Way STE 700 Sunnyvale

Sunnyvale, CA 94089

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Memory and Interfaces for AI and Hyperscale Computing

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Abstract:

Artificial Intelligence has rapidly become the next historically transformative technology, as recent advances in neural networks and the availability of ever more powerful hyperscale computing platforms have broadened AI’s reach and its impact on society. In our increasingly connected world, the needs of data centers, edge computing, and mobile devices are continuing to evolve, and the role of artificial intelligence in each of these locations is evolving as well. But critical challenges remain for enabling higher-performance, more power-efficient, and secure infrastructures supporting AI, all of which offer opportunity for the semiconductor industry. In this seminar, Rambus will discuss some of these challenges, as well as industry directions and potential solutions to support the continued growth of AI and hyperscale computing.

Agenda

6:00 pm Registration opens, networking and food available

6:55 pm Welcome from CASPA

Danny Hua, CASPA President and Chairman of the Board

7:05 pm The Evolving Computing Landscape: How Modern Applications Are Changing the Way We Process Information

Steven Woo, Fellow and Distinguished Inventor, Rambus Labs, Rambus Inc.

7:30 pm High-Performance Interfaces: Choosing the Right Solutions for SoCs

Frank Ferro, Senior Director Product Management, IP Cores, Rambus Inc.

7:55 pm Break

8:05 pm Best Practices for Interface Design Implementation

Arun Vaidyanath, Vice President Engineering, IP Cores, Rambus Inc.

8:30 pm Security Solutions for AI and the Cloud

Neeraj Paliwal, Vice President, Cryptography Products, Rambus Inc.

8:55 pm Closing remarks

9:00 pm Adjourn

Speaker: Steven Woo, Fellow and Distinguished Inventor, Rambus Labs, Rambus Inc.

Speech Title: The Evolving Computing Landscape: How Modern Applications Are Changing the Way We Process Information

Leading-edge applications like Artificial Intelligence (AI), High-Performance Computing (HPC), and the Internet of Things (IoT) generate enormous amounts of digital data, placing tremendous demands on modern computing infrastructures. Looking forward, our ability to meet the needs of future applications will be complicated by the fact that two of the industry’s best tools, Moore’s Law and Dennard Scaling, are either slowing or are no longer available to us to help improve performance and power-efficiency. A new golden age of computer architecture is upon us, as the industry focuses on specialized silicon and new computer and system architectures to meet the demands for higher performance. This presentation will discuss how leading-edge applications are driving change in computing infrastructure, and the crucial role well-designed memory systems and high-speed serial interfaces play in meeting future performance and power-efficiency requirements.

Speaker Bio: Steve works in Rambus Labs on advanced technology and business development efforts across the company. His current focus is on technology and memory systems for accelerators and modern computing infrastructures, including machine learning systems and data centers. Since joining Rambus, Steve has been awarded over 40 US patents, and he has worked in various roles leading architecture, technology, and performance analysis efforts, and in marketing, strategy, and product planning roles. Steve received PhD and MS degrees in Electrical Engineering from Stanford University, and Master of Engineering and BS Engineering degrees from Harvey Mudd College.

Speaker: Frank Ferro, Senior Director Product Management, IP Cores, Rambus Inc.

Speech Title: High-Performance Interfaces: Choosing the Right Solutions for SoCs

Leading-edge, high-performance computation power required by cloud applications is limited by memory and link speed, throughput, and latency. There are a number of options and architectures available to address the needs of AI, High Performance Computing, and hyperscale computing. Each has advantages and tradeoffs that designers and system architects need to consider in order to make the best choice. This presentation will discuss memory and interface options, as well as their characteristics and suitability for leading-edge applications.

Speaker Bio: Frank is currently responsible for memory interface products in our IP Cores group. Having spent more than 20 years at AT&T, Lucent and Agere Systems, he has extensive experience in wireless communications, networking, and the consumer electronics fields. Frank holds an executive MBA from the Fuqua School of Business at Duke University, an M.S. in computer science and a B.S.E.T. in Electronic Engineering Technology from the New Jersey Institute of Technology.

Speaker: Arun Vaidyanath, Vice President Engineering, IP Cores, Rambus Inc.

Speech Title: Best Practices for Interface Design Implementation

There are many design and implementation considerations for successfully integrating the latest memory and interface solutions into high-performance ASICs and SoCs. A system-level approach covering issues such as package design, thermal analysis, channel modeling and board-level design is crucial to a successful implementation. This presentation will cover best practices for implementing memory and serial link interfaces based on Rambus’ many decades of experience designing and implementing interface architectures for the most demanding applications.

Speaker Bio: Arun currently oversees global teams responsible for the development of advanced semiconductor packages and system hardware, the validation of high speed links and memory interfaces, and driving quality in the engineering development for IP Cores products. Arun has over 20 years of experience in signal integrity, system engineering, and semiconductor IP development. He started his career at Tandem Computers, where he led system level signal integrity for fault-tolerant server systems. Arun also drove physical architecture at SiSilk Networks, delivering on and off-chip SI/PI and system/backplane design development. Arun holds a Master's degree in Electrical and Computer Engineering from the University of Arizona.

Speaker: Neeraj Paliwal, Vice President, Cryptography Products, Rambus Inc.

Speech Title: Security Solutions for AI and the Cloud

The demand for trusted applications is on the rise, driven in part by the growing amount of digital data being data housed and processed across connected infrastructures. However, establishing and maintaining trust across an increasingly fragmented ecosystem has proven to be a daunting task. This presentation will cover some of the challenges with implementing trust in servers and data centers, as well as the approach Rambus is taking with our CryptoManager platform and Root of Trust products for AI, cloud, and other use cases. These solutions integrate well with existing server and cloud infrastructure to enable secure provisioning, configuration, keying, and authentication.

Speaker Bio: Neeraj has over 20 years of semiconductor engineering experience in the compute and security domains. At Rambus, Neeraj is responsible for the CryptoManager Secure Silicon IP and Provisioning products. Before joining Rambus, Neeraj founded Kryptos Solutions, where he built an ultra-secure endpoint platform for high-risk government applications. Prior to that, Neeraj was the VP of Engineering at NXP Semiconductors, responsible for major OEM design-wins for NXP’s NFC based secure payment platform. Neeraj has also held various engineering positions at IBM and Intel working on gaming processors, and CPU products. Neeraj graduated with a Master of Technology degree in Solid State Materials from the Indian Institute of Technology in Delhi, India. He also attended the Stanford Executive Program at Stanford University.

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Rambus Inc

1050 Enterprise Way STE 700 Sunnyvale

Sunnyvale, CA 94089

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