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IPC Designers Council - Cascade Chapter Meeting - September

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Lake Washington Institute of Technology

11605 132nd Avenue Northeast

Kirkland, WA 98034

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You are invited to attend the September 20th, 2017 IPC Designers Council Meeting - Cascade Chapter. This event is free but we are accepting cash donations to the Cascade Chapter for future scholarship programs being developed and other Chapter related activities and events.

We will begin the meeting with food and beverages and a chance to network with old friends, meet new friends and other people involved with PCB design.

Our presentation for this meeting will be “DDR2 Design Analysis: On Ramp to High Speed Electronic Design" presented by Craig Arno.



Let’s explore a working high speed DDR2 reference design and analyze the performance impact of a gap in a copper plane between an ARM processor and its DDR2 RAM subsystem. The result of this
analysis is to determine if the system can operate reliably with this gap. Such a gap can be intentional, or an oversight.

Starting with manual analysis in the form of a simple model, equations, and calculation, then perform further simulation using SPICE, then explore IBIS modeling using Altium Designer. Finally, compare
results.

The intent is to demonstrate for implementers and designers some basic high speed design principles. Understanding basic HS design rules can potentially save a project millions of dollars caused by
schedule delay and missed market opportunity.



For more information on this event and other events hosted by the Cascade IPCDC chapter, please visit http://cascade-ipcdc.org

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Date and Time

Location

Lake Washington Institute of Technology

11605 132nd Avenue Northeast

Kirkland, WA 98034

View Map

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