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IEUVI: 3D-EUV STRATEGIC DISCUSSION

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Monterey Marriott

350 Calle Principal

SAN CARLOS ROOM

Monterey, CA 93940

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“Will the advent of 3D monolithic integration eliminate the need for higher lithographic resolution?”

For over 50 years the combination of enhanced lithographic resolution and device structural optimization in conjunction with cell and circuit design cleverness have contributed to increase transistor count on a single die from one technology generation to the next. Aggressive reduction in the number of defects as a function of time has also increased die yield and allowed cost effective manufacturing of progressively larger dice. Finally, the combination of the above factors has enabled growing the number of transistors at Moore’s Law pace for over 50 years; it is anticipated that this trend will continue for the foreseeable future.

Practical limits of dynamic power dissipation for microprocessors were reached by the middle of the past decade and the electronics industry was faced with the realization that both the number of transistors and the operational frequency could no longer be simultaneously increased. Faced with this dilemma the electronics industry decided to continuing following Moore’s Law while limiting any increase in operational frequency to a minimum even though transistors were and continue to be perfectly capable of operating at much higher frequencies.

2D scaling will reach fundamental physical limits by the middle of the next decade and the semiconductor industry is systematically moving towards new revolutionary solutions to overcome this “red brick wall”.

3D monolithic integration of non-volatile memories is already in progress and subsequently 3D monolithic integration of logic and multiple layers of non-volatile memories will allow to continue increasing transistor count at Moore’s Law pace and also enhance computing performance to benchmarking results comparable to previous historical rates.

Most of the reports related to the benefits of 3D monolithic integration indicate that many critical features will be controlled by film deposition and etch parameters rather than by lithographic resolution. In fact, several memory companies have already relaxed many of their lithographic requirements.

Faced once again with a critical dilemma should the electronics industry effort concentrate on 3D monolithic integration or towards lithographic resolution enhancements?

Come and find out what the experts recommend, see you there!

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ROOM SIZE LIMITED TO 80 PEOPLE

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Monterey Marriott

350 Calle Principal

SAN CARLOS ROOM

Monterey, CA 93940

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