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IC Layout Design

Silicon Valley Polytechnic Institute

Monthly Event - Third Monday of every month: 6:00 PM to 9:00 PM (PDT)

San Jose, CA

IC Layout Design

Ticket Information

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Ticket Type Sales End Price Fee Quantity
Tuition plus all fees   more info Dec 23, 2013 $2,950.00 $0.00

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Event Details

This is one the best IC Layout training programs in the industry. It is  part 1 of a 2 course series that covers semiconductor process technologies from 23nm CMOS to 0.35um BCD and explores Analog, Mixed-Signal and RF layout skills. Instructors are seasoned engineers with deep understanding of physical design, class assignments and practice examples are realistic and are taken from actual design projects. Duration of this training program is 12 weeks.

Have questions about IC Layout Design? Contact Silicon Valley Polytechnic Institute

Where



Silicon Valley Polytechnic Institute
1762 Technology Drive, Suite 227
San Jose, CA 95110

Organizer

Silicon Valley Polytechnic Institute

Silicon Valley Polytechnic Institute (SVPTI), dba California Polytechnic Institute (CalPT) is a leading provider of certificate training programs for organizations and working professionals seeking to enhance their skills, employment, and fulfilling their careers in the industry.

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