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Heterogeneous Packaging Integration for Electronics Systems - John H Lau, ASM Pacific Technology

IEEE-Electronics Packaging Society/SCV

Thursday, January 25, 2018 from 11:30 AM to 1:00 PM (PST)

Registration Information

Registration Type Sales End Price Fee Quantity
1: IEEE members-early: Refreshments and Talk
Please enter active IEEE membership number when asked during registration. If student enter STUDENT in member number field, or unemployed enter UNEMPLOY or RETIRE. If sold out please use non-member category.
Jan 24, 2018 $5.00 $1.27
2: non IEEE Members/ late: Refreshments and Talk
Members use this if member category is sold out
Jan 24, 2018 $10.00 $1.53
3: Talk Only - (Please arrive by 11:45am) [IEEE members: please enter membership info when prompted]   more info Jan 25, 2018 Free $0.00
4: Late/ Walk-in *: IEEE members: Refreshments and Talk
*: on food-available basis. talk-only is free.
Not Started $10.00 $1.53
5: Late/ Walk-in: non IEEE Members: Refreshments and Talk
*: on food-available basis. talk-only is free.
Not Started $15.00 $1.78

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Event Details

11:30 AM - 12:00 PM: Check-in / networking - light food
12:00 PM: Presentation
 
Registration [refreshments and talk]:
 
IEEE Members [first 20]:  [also for all students and all unemployed]
  Pre-registration: $  5.00
   [if sold out please use non-IEEE category]
  Walk-in  *:         $10.00     
 
non-IEEE members:
   Pre-registration: $10.00
   Walk-in * :         $15.00
 
*: on a food available basis; talk-only is free any way.
 
[This signs you up for talk too, please do not also register for Talk-Only]

Registration for Talk-Only: FREE
Talk-Only attendees: please check-in by 11:45AM
 

Summary: 

Because of the drive of Moore’s law, compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. It has been a very “fancy” name in semiconductor packaging for the past few years. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem, rather than integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more implementations of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and lower gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

 

SoC: Apple’s application processor (A10 and A11)
SiP: Amkor’s SiP for automobiles; Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer): Leti’s SoW; ULCA’s SoW
Heterogeneous Integration with TSV-Interposers: TSMC/Xilinx’s CoWoS; AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer; Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer: Xilinx/SPIL’s TSV-less SLIT; SPIL/Xilinx’s TSV-less NTI; Amkor’s TSV-less SLIM; ASE’s TSV-less FOCoS; MediaTek’s TSV-less RDLs by FOWLP; Intel’s TSV-less EMIB; Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM; Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer; Cisco/eSilicon’s TSV-less Organic Interposer; ITRI’s TSV-less TSH; Shinko’s TSV-less i-THOP


Bio:

John H. Lau has been a senior technical advisor of ASM since 2014, an ITRI Fellow of Industrial Technology Research Institute for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at HPLab/Agilent in California for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on flip chip technologies, WLCSP, BGA, TSV for 3D integration, advanced MEMS packaging, and reliability of 2D and 3D IC interconnections. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994. 

CPMT   EPS     mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast

Have questions about Heterogeneous Packaging Integration for Electronics Systems - John H Lau, ASM Pacific Technology? Contact IEEE-Electronics Packaging Society/SCV

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When & Where


Texas Instruments Building E Conference Center
2900 Semiconductor Dr.
Santa Clara, CA 95054

Thursday, January 25, 2018 from 11:30 AM to 1:00 PM (PST)


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IEEE-Electronics Packaging Society/SCV

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Heterogeneous Packaging Integration for Electronics Systems - John H Lau, ASM Pacific Technology
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