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FPGA Heterogeneous Packaging Applications: Trends and Challenges: S. Ramalingam, Xilinx, Advanced Pkg Interconnect Tech Dev

IEEE/EPS/SCV

Wednesday, November 14, 2018 from 11:30 AM to 1:00 PM (PST)

Registration Information

Registration Type Sales End Price Fee Quantity
1: IEEE members: Refreshments and Talk
Please enter active IEEE membership number when asked during registration. If student enter STUDENT in member number field, or unemployed enter UNEMPLOY or RETIRE. If sold out please use non-member category.
3h 24m $5.00 $1.27
2: non IEEE Members: Refreshments and Talk
Members use this if member category is sold out
3h 24m $10.00 $1.53
3: Talk Only - (Please arrive by 11:45am) [IEEE members: please enter membership info when prompted]   more info 1d 54m Free $0.00
4: Late/ Walk-in *: IEEE members: Refreshments and Talk
* Online reg starts at 4PM day before event. talk-only is free.
Not Started $10.00 $1.53
5: Late/ Walk-in *: non IEEE Members: Refreshments and Talk
* Online reg starts at 4PM day before event. talk-only is free.
Not Started $15.00 $1.78
Cannot attend this -- PLEASE add name to list for future event notices 22h 54m Free $0.00

Share FPGA Heterogeneous Packaging Applications: Trends and Challenges: S. Ramalingam, Xilinx, Advanced Pkg Interconnect Tech Dev

Event Details

NOTE: Back at TI Auditorium
 
11:30 AM - 12:00 PM: Check-in / networking - PIZZA
12:00 PM: Presentation
 
Registration [refreshments and talk]:
 
IEEE Members:   [also for all students and all unemployed]
  Pre-registration: $  5.00
   [if sold out please use non-MEMBER category]
  Walk-in  *:         $10.00     
 
non-IEEE members:
   Pre-registration: $10.00
   Walk-in * :         $15.00
 
*: on a food available basis; talk-only is free any way.
 
[This signs you up for talk too, please do not also register for Talk-Only]

Registration for Talk-Only: FREE
Talk-Only attendees: please check-in by 11:45AM
 

Summary:

Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.


Bio:

Dr. Suresh Ramalingam  graduated in 1994 with a Ph.D. in Chemical Engineering from the Massachusetts Institute of Technology. He holds 24 US Patents, the 2013 SEMI Award, the Ross Freeman Award for Technical Innovation, ECTC 2011’s Conference Best Paper Award, and IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D. He started his career at Intel developing Organic Flip Chip Technology for microprocessors which was implemented on Pentium I (Intel’s first flip chip product for laptops) in 1997. As one of the co-founders and Director of Packaging Materials at Scion Photonics, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D for Xilinx FPGA products.

 

HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution

Have questions about FPGA Heterogeneous Packaging Applications: Trends and Challenges: S. Ramalingam, Xilinx, Advanced Pkg Interconnect Tech Dev? Contact IEEE/EPS/SCV

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When & Where


Texas Instruments Building E Conference Center
2900 Semiconductor Dr.
Santa Clara, CA 95054

Wednesday, November 14, 2018 from 11:30 AM to 1:00 PM (PST)


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