When: Tuesday, December 3rd, 2019, 11:30am – 5pm

Where:

Conference Room C & D
181 Metro Plaza, Suite 279, San Jose, CA

Note: This is a different location from previous events. Attendance is complimentary, but space is limited, and pre-registration is required.

Sponsored by:

Cadence Designs Systems

AGENDA:

11:30 am - Registration and Lunch

1:00 pm - Presentations

Case Studies

Metrics-Driven Formal Sign-Off of PCIe PCS

Join us for this talk to see how formal sign-off methodology was applied to the Physical Coding Sub-System (PCS) of a PCIe receiver design. Formal sign-off delivers exhaustive coverage required to test all combinations and permutations of input stimulus, including all types and sequences of PCIe ordered sets and framing tokens. This talk will showcase how all design configurations, including asynchronous and plesiochronous clock modes are covered and a metrics-driven approach is used to track progress against the formal sign-off plan.

Presented by: Microchip

Using Formal Sign-off to Deliver Bug-free IPs

For an IP provider, there is always some risk in delivering verified IPs as any issue found within the IP can impact the SoC significantly. But when the IP is a feature rich and highly configurable SoC interconnect solution, the challenges of verifying and delivering a bug free IP gets compounded significantly. With traditional methods of verification getting overwhelmed by complex IPs such as these, companies such as Provino have adopted new methods to ensure their simulation resistant designs have zero bugs. This talk describes how formal sign-off was used to address this challenge and shares how simulation-resistant bugs were eradicated from the design, thereby considerably reducing the risks for the IP users.

Presented by: Provino

Covering the Last Mile in SoC-Level Deadlock Verification

Verifying the absence of System-on-Chip (SoC) deadlocks when integrating a wide variety of Intellectual Property (IP) cores and interconnect fabrics from various internal and third-party sources is a daunting challenge. Current solutions are typically composed of a combination of technologies such as full-chip simulation, emulation and hardware prototyping. However, deadlock scenarios often occur in rare cases that involve several preconditions occurring in sequence and with specific timing. Consequently, deadlock bugs may only be triggered in extreme corner-case conditions, which are resistant to discovery by traditional methods. This talk describes a formal solution that exploits the exhaustive nature of formal analysis to overcome this resistance and deliver the confidence required for sign-off.

Presented by: U-blox

4:00 pm - Networking Reception

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