IEEE Computer Society Chapter of Silicon Valley Monthly Technical Meeting

Multicore, the Memory Wall, and Numerical Compression

IEEE Computer Society of Silicon Valley

Wednesday, April 11, 2012 at 6:30 PM - Wednesday, December 31, 2014 at 9:00 PM (PDT)

San Jose, CA

Ticket Information

Type End     Quantity
On-Demand Webcast
This ticket goes live a few days after the event. After registration you will receive be able to view the webcast. (Microsoft SILVERLIGHT required)
Dec 31, 2014 Free  
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Event Details


of Silicon Valley Presents:

Multicore, the Memory Wall, and Numerical Compression

 

 

Speaker:    Al Wegener, Chairman and CTO, Samplify Systems

Location:   Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (Building 10 map)

When:         Apr. 11:  6:30 pm Networking with food and beverage
                                     7:00 pm Presentation

Registration:     Free – but Please Register      [ $2 donation helps cover food ]
                                                                                    [ Please bring your PDF ticket ]

Webcast: To access the live webcast, use the webcast ticket above, and...
    • Live webcast 'ticket' goes active at 6:30 PM, broadcasting begins at 7:00 PM
    • A link to the webcast will be provided in the registration confirmation page.
    • Microsoft's Silverlight is required to view this. To install it click here.
 

Abstract:

Why is multicore processor utilization decreasing?  A worrying trend has emerged in supercomputing, which deploys thousands of multicore CPU and GPU sockets for big data applications, foreshadowing future problems with multicore. As a percentage of peak Mflops, today’s supercomputers are less than 10% utilized. The reason is simple: input-output (I/O) has not nearly kept pace with multicore MIPS.  While cores per die scales with Moore's Law, interconnect to off-chip memory, system busses, networks, and disk drives does not.  Multicore CPUs and GPUs are hitting the memory wall.  We present a novel numerical compression algorithm for integers, floating-point values, still images, and video that increases DDRx, PCIe, Ethernet, and SAS/SATA bandwidth by 2x to 6x at wire speeds, with complete user control and without changing the final results of the computation. 

Bio:

Al Wegener is the CTO, chairman and founder of Samplify Systems, a venture-funded IP licensing start-up whose compression and acceleration products reduce bandwidth and storage bottlenecks in electronic systems.  Samplify's products offer lossless, fixed-rate and fixed-quality compression modes that users control in real time.  Mr. Wegener has developed products for wireless, pro and consumer audio, and defense applications.  Mr. Wegener holds an MSCS from Stanford University, a BSEE from Bucknell University, and is named on 30+ U. S. patents. 


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Thanks to those sponsoring part of our pizza this meeting:


Altera


TBD – Recruiters like sponsoring us…
TBD – Your company here…
TBD – Providing services…

When & Where


Cadence Design Systems, Bldg 10
Montague Expy & Trimble Road
San Jose, CA 95134

Wednesday, April 11, 2012 at 6:30 PM - Wednesday, December 31, 2014 at 9:00 PM (PDT)


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