of Silicon Valley Presents:
Mixing HW & SW Successfully
Speaker: Stuart Swan, Senior Architect Systems Solutions Group, Cadence
Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (Building 10 map)
When: Mar. 13: 6:30 pm Networking with food and beverage
7:00 pm Presentation
Registration: Free – but Please Register [ $2 donation helps cover food ]
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The scale and complexity of chip design has exploded in the last twenty years. Starting with a brief review of the hardware design and verification techniques used over the last two decades, this presentation will explore how chips have evolved into System on Chips (SoCs), and will explore the emergence of new design and verification techniques to tackle the complexity of today’s SoCs, which frequently include multiple processors, embedded software, and complex communication protocols. We will then explore some new design and verification techniques for SoCs that are likely to become prevalent in the near future.
Stuart Swan is a Senior Architect in the Systems Solutions Group at Cadence Design Systems, and has over twenty years of experience in the EDA industry. Mr. Swan helped create a number of new EDA tools at Cadence and has worked directly with SoC designers at large customers around the world to help them adopt new tools and methodologies. In the area of SoC modeling standards, he helped lead development of System-C and authored a book, served in the OSCI/Accellera board of directors, and was technical working group chairman for the IEEE SystemC LRM development. He has also been active in the development and standardization of the SystemVerilog OVM and UVM verification methodologies. Stuart graduated from Stanford University with a BSEE with honors.
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Thanks to those sponsoring part of our pizza this meeting:
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