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IEEE Computer Society Chapter of Silicon Valley Monthly Technical Meeting

SPARC 3.6 GHz Processor: a 16-core, 128 threaded SoC

IEEE Computer Society of Silicon Valley

Tuesday, August 13, 2013 at 6:30 PM (PDT)

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Live Webcast
This ticket goes live at 6:00pm on the event date. Our broadcast goes live at 7:00 PM. (Microsoft SILVERLIGHT required)
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Event Details

of Silicon Valley Presents:


SPARC 3.6 GHz Processor: 

a 16-core, 128 threaded SoC


Date: Tuesday, August 13, 2013

Speaker: Jason Hart, Senior Principal Hardware Engineer, Oracle Corporation

Time: 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation

Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map)


The 3.6 GHz T5 processor is Oracle's next- generation CMT SPARC processor implemented in TSMC's 28nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generation's number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3x. Power efficiency was improved through features like DVFS, core pair cycle skipping and SerDes power scaling.

This presentation will give a brief summary of the processor and core architecture and features. The physical composition will be covered including the library cell swapping and characterization methodologies. A look at the new power management features will be followed by power distribution and clock distribution, including a look at the frequency-locked loop and clock multiplexor. We will look at the L3 cache and its repair mechanisms. Then we will conclude with the SerDes Wide Band Amplifier. 


Speaker Bio

Jason Hart received the B.S. degree in electrical engineering from the University of Idaho, Moscow. He joined Sun Microsystems, Inc. in 1995 after working in Product Engineering at Micron Technology, Boise, ID. Jason has been doing circuit design, global circuits and composition for UltraSPARC I, III, IV+ and now Oracle’s T5. Design work has included SRAM’s, register files, static and dynamic custom circuits, libraries, timing, FGU composition, and responsibility for clocking on T5. 

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Have questions about SPARC 3.6 GHz Processor: a 16-core, 128 threaded SoC? Contact IEEE Computer Society of Silicon Valley

When & Where

Cadence Design Systems, Bldg 10
Montague Expy & Trimble Road
San Jose, CA 95134

Tuesday, August 13, 2013 at 6:30 PM (PDT)

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