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IEEE Tutorial on LDPC Decoding: VLSI Architectures and Implementations

IEEE-SCV-PACE, SPS, ITS, CAS, SSCS, ComSoC and Magnetics society

Wednesday, August 6, 2014 from 7:00 PM to 9:30 PM (PDT)

Santa Clara, CA

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Walk-In Registration Ended $50.00 $3.49

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Event Details

Abstract:

LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD. Tutorial’s target audience is system engineers and design engineers. Tutorial has two parts, first module is focused on LDPC Decoding and second module is focused on VLSI Architectures and Implementations. IEEE Standard draft LDPC codes for Flash memories also will be covered.

 

Tutorial overview

Module 1 LDPC Decoding

1.1) LDPC codes

1.2) Hard decision decoding,

1.3) LLR basics and LLR generation for soft decoding for Flash memory channel

1.4) Soft decoding and Min-Sum Algorithm

1.5) LDPC decoder performance characteristics, trapping sets and error floor

1.6) Basics of Code Structures for Efficient hardware.

 

 

Module 2 VLSI Architectures and Implementations

2.1) Check Node Unit Design and Value-reuse property

2.2)   Non-layered decoder architecture

a)   Block serial processing

b)  Translating throughput requirement to H matrix parameters and edge parallelization

2.3)  Layered decoder architecture

 a) Block serial processing

 b) Block serial processing for irregular H matrices, scheduling of decoder processing

 c) Block parallel processing

 d) Translating throughput requirement to H matrix parameters and edge parallelization

 e) Case study of decoders for IEEE P1890 Standards draft LDPC codes

 

(P1890-Standards Working Group on Error Correction Coding for Non-Volatile Memories)


2.4) Error floor mitigation schemes

 

Speakers

Module 1:

Ned Varnica, Marvell Semiconductor

 

Ned Varnica received the B.S. degree in Electrical Engineering in 2000 from School of Electrical Engineering, University of Belgrade, Serbia, the M.S. degree in 2001 and Ph.D. in 2005 both from Harvard  University, Cambridge, Massachusetts. 

Since 2005 he has been with Marvell Semiconductor Inc, Santa Clara, California. He held short-term research positions at Maxtor Corporation, Shrewsbury, Massachusetts in 2002 and Lucent Bell Labs, Murray Hill, New Jersey in 2004. He spent the summer of 2003 as a visiting researcher at University of Hawaii at Manoa, Honolulu. His research interests are in the areas of communication theory, information theory, channel and source coding and their applications to digital data storage and wireless communications.

Dr. Varnica received the Best Student of the Class Award from the Department of Communications at the School of Electrical Engineering, University of Belgrade in 2000.  He is a co-recipient, with A. Kavcic and X. Ma, of the 2005 IEEE Best Paper Award in Signal Processing and Coding for Data Storage.

 

 

Module 2:

Kiran Gunnam, HGST Research

 

Kiran Gunnam received the MSEE and PhD in Computer Engineering from Texas A&M University, College Station, TX. He currently works as a Technologist at HGST Research.  He previously worked as Director of Engineering at Violin Memory and also held R&D positions at Nvidia, Certicom, LSI, Marvell, Schlumberger, and Intel.

Dr. Gunnam has extensive research and development work experience in complex data path and control path systems. Dr. Gunnam is an expert in IC implementation of communications and signal processing systems. His PhD research contributed several key innovations in advanced error correction systems based on low-density parity- check codes (LDPC) and led to several industry designs. He has done extensive work on ASIC hardware architecture, micro-architecture and digital IC implementation for different systems (IEEE 802.11n Wi-Fi, IEEE 802.16e WiMax, IEEE 802.3 10-GB, Holographic read channel, HDD read channel and Flash read channel).

Dr. Gunnam has around 54 issued US patents and several pending patents and invention disclosures. He is the lead inventor/sole inventor for 90% of them. He is an IEEE Senior Member. He is also an IEEE Solid State Circuits Society Distinguished Lecturer for 2013 and 2014.

 

Event Co-sponsors:

Flash Memory Summit

www.flashmemorysummit.com/

IEEE Professional Activities Committee for Engineers, Santa Clara Valley Section (IEEE SCV PACE)

http://sites.ieee.org/scv-pace/

Have questions about IEEE Tutorial on LDPC Decoding: VLSI Architectures and Implementations? Contact IEEE-SCV-PACE, SPS, ITS, CAS, SSCS, ComSoC and Magnetics society

When & Where


Flash Memory Summit Conference, Santa Clara Convention Center, Santa Clara
5001 Great America Parkway
Santa Clara, CA 95054

Wednesday, August 6, 2014 from 7:00 PM to 9:30 PM (PDT)


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Organizer

IEEE-SCV-PACE, SPS, ITS, CAS, SSCS, ComSoC and Magnetics society

IEEE Santa Clara Valley Section (Silicon Valley Section) :

Professional Activities Committes for Engineers (PACE)

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