IEEE Short Course on "Signal Integrity in High Speed Data Link"
Thursday, May 16, 2013 from 5:30 PM to 9:00 PM (PDT)
Santa Clara, CA
San Francisco, California
London, United Kingdom
"There are two types of designers: Those that have signal-integrity problems and those that will." (Sun Microsystems)
The high speed designs continue to experience major technology advancements while parallel high speed data links are exceed 100Gbps range. Therefore, the interconnect losses, frequency depended channel characteristic and other timing parameters needs to be understood and considered during the design phase.
The concept of signal integrity for high speed circuit and high speed data link will be covered in this tutorial.
The course objectives are developing the skill for analyzing high speed circuits, understanding signal integrity and terminology associated with it. The loss compensation techniques will be discussed in this course while interconnect modeling and loss are taking into consideration.
The outline for the tutorial is as follow:
1. Introduction to high-speed link
2. Introduction to signal integrity
3. Signal and Timing parameters
4. Transmission line: cross-talk, loss and modeling
5. Channel loss and compensation (Equalization)
6. Continuous Time Linear Equalizer (CTLE)
7. Decision Feedback Equalizer (DFE)
9. Used case: challenges in PCIe 4.0 data link
Eventbrite registration is mandatory for every one to attend the short course.
Texas Instrument employees should register for "Texas Instruments Employee" free ticket and are eligible for free admission with TI badge.
Venue: Texas Instruments Silicon Valley Auditorium (previously National Semiconductor), 2900 Semiconductor Dr., Santa Clara, CA 95051
Time: May 16th (Thursday) evening 5.30pm-8.30pm.
Networking and snacks : 5:30 PM: 6:00 PM ;
Lecture Time, Session 1 : 6.00 PM- 7.00 PM
Break : 7.00PM- 7.15PM ;
Lecture Time, Session 2 : 7.15 PM -8.15 PM
Overflow questions : 8:15 PM -8.45 PM ;
Event conclusion : 8.45PM -9 PM
Shahab Ardalan (M’02, SM’10) completed his B.Sc. at Amirkabir University of Technology, Iran in 1999, and his PhD degree at the University of Waterloo, Waterloo, Canada in 2007. Dr. Ardalan joined analog mixed signal research and development group in Gennum Corp. in 2007 where he was continuing his research activities on low-power, low-voltage circuits for high speed data and video broadcasting. In 2010, Dr. Ardalan joined San Jose State University as an assistant professor and director of center for analog and mixed signal where he is teaching and conducting research on topics of analog and mixed signal integrated circuits and integrated circuit security.
Dr. Ardalan’s research has led to several publications including more than 15 IEEE papers. He is the recipient of the best paper award of ICUE’04 and the CMC Industrial Award from strategic Microelectronic Council of ITAC in 2005. Dr. Ardalan was holding a postgraduate scholarship from National Science and Engineering Research Council of Canada (NSERC) from 2004-2007 and NSERC post-doctoral fellowship award in 2010. He has been member of technical and organizing committee for number IEEE conferences. He was member of IEEE Canada board of executive from 2004-2012 and chair of solid state circuit society in Kitchener/Waterloo chapter.