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Electronic Design Process Symposium (EDPS)

IEEE Computer Society of Silicon Valley

Thursday, April 7, 2011 at 9:00 AM - Friday, April 8, 2011 at 1:00 PM (PDT)

Monterey, CA

Electronic Design Process Symposium (EDPS)

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nonIEEE Member Registration
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Event Details

     

 

18th Annual

Electronic Design Process Symposium

April 7 & 8, 2011

Monterey Beach Hotel, Monterey, CA

Sponsored by the

IEEE Computer Society Chapter of Silicon Valley
and

C
ouncil on Electronic Design Automation (CEDA)
and the
Design Automation Technical Committee (DATC)

 

Corporate Sponsor:

The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves. Visit www.eda.org/edps to see a list of past EDPS speakers and presentations.

Session Themes:

  • Parallel EDA
  • High-Level Design - including Requirements-Driven Design Flows
  • Cloud computing - including Software as a Service
  • Low-Power Design - with Solution Mapping to 2009 ITRS Roadmap
  • 3D ICs

On site Registration available April 7 & 8 - bring a check (no credit cards).

  • Registration includes a copy of the workshop notes, continental breakfast on both days, lunch both days, and the EDP banquet dinner.
  • You may bring a guest to the Banquet Dinner for $50.00. If you do, please pay when you first check into the meeting.

Important Web Sites:

www.eda.org/edps
www.montereybeachresort.com

Preliminary Schedule:

   Thursday, April 7
     
9:00 AM  Keynote Rob Aitken Low Power Advancements in Embedded Design ARM
10:00 AM  Break      
10:15 AM  Session 1
Parallel EDA
 
    Kevin Cameron Designing An ESL Language - the thinking behind ParC CameronEDA
    Juan Rey Many-companies vs. Many-core: cooperative/competitive framework to tame the challenges we all face Mentor
    Dipanjan Gope Multilevel Parallelization Architecture of Boundary Element Solver Engines for Cloud Computing Physware
    Bill Swartz On Advancing the State of Parallel CAD Algorithms InternetCAD
12:15 PM  Lunch Naresh Sehgal Some Security Challenges with Cloud Computing Intel
1:30 PM  Session 2
Cloud, SaaS, High Level Design
 
    James Colgan Cloud Implementation - Looking Beyond the Servers Xuropa
    Steve Leibson EDA360: Is End-to-End Design a Riddle, a Rebus, or a Reality? Cadence
    Valerie Rachko Requirements Driven Design Flows Including DO254 Mentor
3:00 PM  Break      
3:30 PM  Session 3
Low Power & New Frontiers
 
    Ed Grochowski RTL Design on a Laptop, Proof-of-Concept Experiment Results Intel
    Mike Rieger Challenges in the pattern-transfer information channel Synopsys
    Bhanu Kapoor (low power) Mimasic
5:30 PM  Break      
6:00 PM  Keynote
 & dinner
Lucio Lanza   Lanza Tech Ventures
   Friday, April 8
     
9:00 AM  Keynote Raul Composano Design Technology in the Cloud Physware
10:00 AM  Break      
10:15 AM  Session 4
3D–ICs
 
    Biswadeep Chatterjee Taxonomy Based Interactive Resource Allocation System Intel
    Herb Reiter Paradigm shift to 3D and its impact on design tools, standards and our ecosystem EDA2ASIC
    Rahul Deokar What are the EDA design tool requirements to support 3D-IC Design Cadence
    Karen Chow 3D-IC System Verification Methodology: Solutions and Challenges  Mentor
         
   
Panel: 3D-IC's Real or Imaginary:
What Would Speed Adoption
 
12:15 PM  Panel
 & lunch
Herb Reiter,
moderator
3D-IC's: Real or Imaginary: what would speed adoption? EDA2ASIC
    Dusan Petranovic Panelist Mentor
    TBD Panelist  
    TBD Panelist  
    TBD Panelist  
1:30 PM  Wrap-up Naresh & John Get Attendees feedback and announce plans for EDPS 2012

 

Have questions about Electronic Design Process Symposium (EDPS)? Contact IEEE Computer Society of Silicon Valley

When & Where


Monterey Beach Resort Hotel

Monterey, CA

Thursday, April 7, 2011 at 9:00 AM - Friday, April 8, 2011 at 1:00 PM (PDT)


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